A TDC is a device that provides a digital representation of a time duration at which an event occurs. A TDC determines an interval of time between two signal pulses (e.g., a start pulse and a stop pulse).
A typical all-digital phase-locked loop (ADPLL) includes a TDC, a digital loop filter, a digitally-controlled oscillator (DCO), and a divider. The TDC may introduce quantization noise to the ADPLL. As a result, a high-resolution TDC is desired for a low-phase noise ADPLL. An analog-to digital converter (ADC) may be used to improve the resolution of a TDC.
A digital PLL architecture may take the form of a typical ΔΣ fractional-N PLL which converts both positive and negative phase errors. A flip-flop may detect a phase error polarity based on the relative timing of “up” and “down” rising edges. A two-input XOR-gate may generate a pulse with duration representing a magnitude of the phase error. The ability to measure both positive and negative phase errors reduces a lock time. A digital PLL may be implemented in a 14 nanometer (nm) fin field effect transistor (FINFET) complementary metal oxide semiconductor (CMOS) process, and may be incorporated into a cellular radio frequency integrated circuit (RFIC).